Turning to FIG. 1, an example of a conventional Rth-order SDM 100 can be seen. This SDM 100 generally comprises integrators 102-1 to 102-R coupled in series with one another, a quantizer 104 (which generally includes a latched comparator and a D flip-flop) that is coupled to integrator 102-R, and digital-to-analog converters (DACs) 106-1 to 106-R (which are respectively associated and coupled to integrators 102-1 to 102-R). As shown, SDM 100 generates digital output signals OUT from a differential input signal INP and INM; consequently, integrators 102-1 to 102-R each have a positive path (which respectively includes resistors RP-1 to RP-R and capacitors CP-1 to CP-R) and a negative path (which respectively includes resistors RM-1 to RM-R and capacitors CM-1 to CM-R) that are respectively coupled to amplifiers 108-1 to 108-R. The DACs 106-1 to 106-R (which are current steering DACs) then provide adjustments (i.e., currents) to the positive and negative paths of integrators 102-1 to 102-R (respectively) based on an output of a comparator within the quantizer 104.
Each DAC 106-1 (hereinafter 106) generally comprises several DAC switches 202-1 to 202-N (which can be seen in FIG. 2). Each of these DAC switches 202-1 to 202-N provides a predetermined current (from its current source 204-1 to 204-N) to its positive and negative paths (hereinafter VP and VM, respectively). The directions of these predetermined currents are based on the configuration of switches SP-1 to SP-N and SM-1 to SM-N (which are controlled by the control signal X[n]). A problem with this arrangement is that there is both an imbalance between switch pairs SP-1/SM-1 to SP-N/SM-N in DAC switches 202-1 to 202-N due to offsets and a parasitic capacitances CPAR-1 to CPAR-N that results in a large spur at the second harmonic (as shown in FIG. 3). Therefore, there is a need for an improved SDM.
Some examples of conventional circuits are: U.S. Pat. No. 5,729,230; U.S. Pat. No. 7,324,028; U.S. Pat. No. 7,405,687; Bolatkale et. al., “A 4 GHz CT ΔΣ ADC with 70 dB DR and −74 dBFS THD in 125 MHz BW,” ISSCC Dig. Tech. Papers, pp. 470-471, February 2011; Mitteregger et. al., “A 14b 20 mW 640 MHz CMOS CT ΣΔ ADC with 20 MHz Signal Bandwidth and 12b ENOB,” ISSCC Dig. Tech. Papers, pp. 62-63, February 2006; Park et al., “A 0.13 μm CMOS 78 dB SNDR 87 mW 20 MHz BW CT ΔΣ ADC with VCO-based Integrator and Quantizer,” ISSCC Dig. Tech. Papers, pp. 170-171, February 2009; Ke et al., “A 2.8-to-8.5 mW GSM/BlueTooth/UMTS/DVB-H/WLAN Fully Reconfigurable CT ΔΣ with 200 KHz to 20 MHz BW for 4G radios in 90 nm digital CMOS,” IEEE Symposium on VLSI Circuits, pp. 153-154, 2010; Balachandran et. al., “A 1.16 mW 69 dB SNR (1.2 MHz BW) Continuous-Time ΣΔ ADC with Immunity to Clock Jitter,” IEEE Custom Integrated Circuits Conference, September 2010; Oliaei, “Sigma-Delta Modulators with Spectrally Shaped Feed-Back,” IEEE Transactions on Circuits and Systems II, Vol. 50, No. 9, pp. 518-530, September 2003; and Singh et al., “Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous Time Delta Sigma Modulators,” IEEE Transactions on Circuits and Systems II, Vol. 57, Issue 9, pp. 676-680, September 2010.